IS61SF25616 Datasheet, PDF (3/16 Pages) Integrated Silicon Solution, Inc – 256K x 16, 256K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM

IS61SF25616
IS61SF25618
PIN CONFIGURATION
ISSI ^®
119-pin PBGA (Top View)
1
2
3
4
5
6
7
A
VCCQ A6
A4 ADSP A8
B
NC
CE2
A3 ADSC A9
C
NC
A7
A2
VCC A12
D
DQ9
NC
GND
NC
GND
E
NC
DQ10 GND
CE
GND
F
VCCQ NC
GND
OE
GND
G
NC
DQ11 BW2 ADV GND
H
DQ12
NC
GND GW GND
J
VCCQ VCC
NC
VCC
NC
K
NC
DQ13 GND CLK GND
L
DQ14
NC
GND
NC
BW1
M
VCCQ DQ15
GND
BWE
GND
N
DQ16
NC
GND
A1
GND
P
NC
NC
GND
A0
GND
R
NC
A5 MODE VCC GND
T
NC
A11
A10
NC
A14
U
VCCQ NC
NC
NC
NC
A16
CE2
A15
NC
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
100-Pin TQFP
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
GND
VCC
NC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
NC
NC
GND
VCCQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A17
NC
NC
VCCQ
GND
NC
NC
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
256K x 16
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BW1-BW2
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQ1-DQ16 Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply: +3.3V
ZZ
Snooze Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. A
04/17/01