IS62WV5128DALL Datasheet, PDF (8/18 Pages) Integrated Silicon Solution, Inc – 512K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
35 ns 45 ns 55 ns
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max. Unit
trc
Read Cycle Time
35 —
45 —
55 —
ns
taa
Address Access Time
— 35
— 45
— 55
ns
toha
Output Hold Time
10 —
10 —
10 —
ns
tacs1
CS1 Access Time
— 35
— 45
— 55
ns
tdoe
OE Access Time
— 10
— 20
— 25
ns
thzoe⁽²⁾
OE to High-Z Output
— 10
— 15
— 20
ns
tlzoe⁽²⁾
OE to Low-Z Output
3
—
5—
5
—
ns
thzcs1
CS1 to High-Z Output
0 10
0 15
0 20
ns
tlzcs1
CS1 to Low-Z Output
5
—
10 —
10 —
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1^(1,2) (Address Controlled) (CS1 = OE = Vil, WE = Vih)
ADDRESS
DOUT
tRC
tAA
tOHA
PREVIOUS DATA VALID
tOHA
DATA VALID
8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.  A
02/09/2012