IS62WV5128DALL Datasheet, PDF (10/18 Pages) Integrated Silicon Solution, Inc – 512K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
35ns 45ns 55 ns
Symbol
Parameter
Min. Max.
Min. Max. Min. Max. Unit
twc
Write Cycle Time
35 —
45 —
55 — ns
tscs1
CS1 to Write End
25 —
35 —
45 — ns
taw
Address Setup Time to Write End 25 —
35 —
45 — ns
tha
Address Hold from Write End
0—
0—
0 — ns
tsa
Address Setup Time
0—
0—
0 — ns
tpwe
WE Pulse Width
25 —
35 —
40 —ns
tsd
Data Setup to Write End
20 —
20 —
25 — ns
thd
Data Hold from Write End
0—
0—
0 — ­ns
thzwe⁽³⁾
WE LOW to High-Z Output
— 10
— 20
— 20 ns
tlzwe⁽³⁾
WE HIGH to Low-Z Output
3—
5—
5 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW)
ADDRESS
CS1
tWC
tSCS1
tHA
WE
DOUT
DIN
tAW
tPWE
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.  A
02/09/2012