IS43DR16320 Datasheet, PDF (8/29 Pages) Integrated Silicon Solution, Inc – Clock frequency up to 400MHz

IS43DR86400, IS43/46DR16320
time (tMRD) must be satisfied to complete the write operation to the extended mode register 2. Mode register contents can be
changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state.
Extended Mode Register 2 (EMR[2]) Diagram
Address
Field
BA1
BA0
A13⁽¹⁾
A12⁽¹⁾
Mode
Register
1
0
0
0
A11⁽¹⁾
0
A10⁽¹⁾
0
A9⁽¹⁾
0
A8⁽¹⁾
0
A7
SRFt
A6⁽¹⁾
0
A5⁽¹⁾
0
A4⁽¹⁾
0
A3⁽¹⁾
0
A2
A1
PASR⁽³⁾
A0
A7
High Temperature Self-Refresh Rate Enable
0
Disable
1
Enable⁽²⁾
A2
A1
A0
Partial Array Self Refresh for 8 Banks
0
0
0
Full Array
0
0
1
Half Array(BA[2:0]=000, 001, 010, 011)
0
1
0
Quarter Array(BA[2:0]=000, 001)
0
1
1
1/8 array(BA[2:0]=000
1
0
0
3/4 array(BA[2:0]=010, 011, 100, 101, 110, 111)
1
0
1
Half array(BA[2:0]=100, 101, 110, 111)
1
1
0
Quarter array(BA[2:0]=110, 111)
1
1
1
1/8 array(BA[2:0]=111
Notes:
1. A3‐A6, and A8‐A13 are reserved for future use and must be set to 0 when programming the EMR[2].
2. Only Industrial and Automotive grade devices support the high temperature Self‐Refresh Mode. The controller can set the EMR (2) [A7] bit to enable this self‐
refresh rate if Tc > 85°C while in self‐refresh operation. TOPER may not be violated.
3. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh is entered. Data
integrity will be maintained if tREF conditions are met and no Self Refresh command is issued.
DDR2 Extended Mode Register 3 (EMR[3]) Setting
No function is defined in extended mode register 3. The default value of the extended mode register 3 is not defined. Therefore, the
extended mode register 3 must be programmed during initialization for proper operation.
Integrated Silicon Solution, Inc. – www.issi.com –
8
Rev. 00A, 11/17/2009