IS65C256AL_12 Datasheet, PDF (7/12 Pages) Integrated Silicon Solution, Inc – 32K x 8 LOW POWER CMOS STATIC RAM

IS65C256AL
IS62C256AL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol
tWC
tSCS
tAW
tHA
tSA
tPWE1,
tPWE2⁽⁴⁾
tSD
tHD
Parameter
-25 ns
-45 ns
Min. Max.
Min. Max.
Unit
Write Cycle Time
CE to Write End
25 —
45 —
ns
15 —
35 —
ns
Address Setup Time to Write End
15 —
25 —
ns
Address Hold from Write End
0—
0—
ns
Address Setup Time
WE Pulse Width
0—
0—
ns
15 —
25 —
ns
Data Setup to Write End
Data Hold from Write End
12 —
20 —
ns
0—
0—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) ^{(1 )}
ADDRESS
CE
WE
DOUT
DIN
t WC
VALID ADDRESS
t SA
t SCS
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
CS_WR1.eps
Integrated Silicon Solution, Inc.
7
Rev. D
05/09/12