IS62LV256L-15T Datasheet, PDF (7/7 Pages) Integrated Silicon Solution, Inc – 32K x 8 LOW VOLTAGE CMOS STATIC RAM

IS62LV256L
WRITE CYCLE NO. 2 (CE Controlled)^(1,2)
ADDRESS
CE
WE
DOUT
DIN
tWC
tSA
tSCE
tHA
tAW
tPWE
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
ISSI ^®
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ VIH.
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
15
20
25
Order Part No.
IS62LV256L-15T
IS62LV256L-15J
IS62LV256L-20T
IS62LV256L-20J
IS62LV256L-25T
IS62LV256L-25J
Package
450-mil TSOP
300-mil Plastic SOJ
450-mil TSOP
300-mil Plastic SOJ
450-mil TSOP
300-mil Plastic SOJ
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
15
20
25
Order Part No.
IS62LV256L-15TI
IS62LV256L-15JI
IS62LV256L-20TI
IS62LV256L-20JI
IS62LV256L-25TI
IS62LV256L-25JI
Package
450-mil TSOP
300-mil Plastic SOJ
450-mil TSOP
300-mil Plastic SOJ
450-mil TSOP
300-mil Plastic SOJ
ISSI ^®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: [phone]
Fax: [phone]
E-mail: [e-mail]
www.issi.com
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