IS62C51216AL Datasheet, PDF (7/15 Pages) Integrated Silicon Solution, Inc – 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS62C51216AL, IS65C51216AL
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol
Parameter
45 ns
55 ns
70 ns
Min. Max.
Min. Max.
Min. Max.
Unit
trc
Read Cycle Time
45
—
55
—
70
—
ns
taa
Address Access Time
—
45
—
55
—
70
ns
toha³
Output Hold Time
10
—
10
—
10
—
ns
tacs1/tacs2
CS1/CS2 Access Time
—
45
—
55
—
70
ns
tdoe
OE Access Time
—
20
—
25
—
35
ns
thzoe⁽²⁾
OE to High-Z Output
—
15
—
20
—
25
ns
tlzoe⁽²⁾
OE to Low-Z Output
5
—
5
—
5
—
ns
t t hzcs1/ hzcs2⁽²⁾ CS1/CS2 to High-Z Output
0
15
0
20
0
25
ns
t t lzcs1/ lzcs2⁽²⁾ CS1/CS2 to Low-Z Output
10
—
10
—
10
—
ns
tba
LB, UB Access Time
—
45
—
55
—
70
ns
thzb
LB, UB to High-Z Output
0
15
0
20
0
25
ns
tlzb
LB, UB to Low-Z Output
0
—
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.10ns for CMOS Loading. 8ns @ AC Loading.
AC WAVEFORMS
READ CYCLE NO. 1^(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih, UB or LB = Vil)
ADDRESS
DQ0-D15
tRC
tAA
tOHA
PREVIOUS DATA VALID
tOHA
DATA VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev.  A
03/18/09