IS61VPD25636A Datasheet, PDF (7/32 Pages) Integrated Silicon Solution, Inc – 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

IS61VPD25636A, IS61VPD51218A, IS61LPD25636A, IS61LPD51218A
ISSI ^®
165 PBGA PACKAGE PIN CONFIGURATION
512K X 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
A
NC
A
B
NC
A
CE
CE2
BWb
NC
NC
BWa
CE2
CLK
BWE
GW
ADSC ADV
A
OE
ADSP A
C
NC
NC
VDDQ
Vss
Vss
Vss
Vss
Vss
VDDQ
NC
D
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
E
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
F
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
G NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
H
NC
Vss
NC
VDD
Vss
Vss
Vss
VDD
NC
NC
J
DQb NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
K
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
L
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
M DQb NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
N
DQPb NC
VDDQ
Vss
NC
NC
NC
Vss
VDDQ
NC
P
NC
NC
A
A
TDI
A1*
TDO A
A
A
R
MODE NC
A
A
TMS A0*
TCK A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is
desired.
11
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a,b)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQx
DQPx
VDD
VDDQ
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V/2.5V
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
05/09/05