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IS61VPD25636A Datasheet, PDF (15/32 Pages) Integrated Silicon Solution, Inc – 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM | |||
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IS61VPD25636A, IS61VPD51218A, IS61LPD25636A, IS61LPD51218A
ISSI ®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-250
Min. Max.
-200
Min. Max.
Unit
fMAX Clock Frequency
â
250
â
200
MHz
tKC
Cycle Time
4.0
â
5
â
ns
tKH
Clock High Time
1.7
â
2
â
ns
tKL
Clock Low Time
1.7
â
2
â
ns
tKQ
Clock Access Time
â
2.6
â
3.1
ns
tKQX(2) Clock High to Output Invalid
0.8
â
1.5
â
ns
tKQLZ(2,3) Clock High to Output Low-Z
0.8
â
1
â
ns
tKQHZ(2,3) Clock High to Output High-Z
â
2.6
â
3.0
ns
tOEQ Output Enable to Output Valid
â
2.6
â
3.1
ns
tOELZ(2,3) Output Enable to Output Low-Z
0
â
0
â
ns
tOEHZ(2,3) Output Disable to Output High-Z
â
2.6
â
3.0
ns
tAS
Address Setup Time
1.2
â
1.4
â
ns
tWS Read/Write Setup Time
1.2
â
1.4
â
ns
tCES Chip Enable Setup Time
1.2
â
1.4
â
ns
tAVS Address Advance Setup Time
1.2
â
1.4
â
ns
tDS
Data Setup Time
1.2
â
1.4
â
ns
tAH
Address Hold Time
0.3
â
0.4
â
ns
tWH
Write Hold Time
0.3
â
0.4
â
ns
tCEH Chip Enable Hold Time
0.3
â
0.4
â
ns
tAVH Address Advance Hold Time
0.3
â
0.4
â
ns
tDH
Data Hold Time
0.3
â
0.4
â
ns
tPDS ZZ High to Power Down
â
2
â
2
cyc
tPUS ZZ Low to Power Down
â
2
â
2
cyc
Note:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. â 1-800-379-4774
15
Rev. A
05/09/05
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