IS61NLF12836A Datasheet, PDF (7/27 Pages) Integrated Silicon Solution, Inc – 128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
ISSI ^®
119-PIN PBGA PACKAGE CONFIGURATION 256K x 18 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
A
NC
A
A
VDDQ
B
NC
CE2
A
ADV
A
CE2
NC
C
NC
A
A
VDD
A
A
NC
D DQb
NC
VSS
NC
Vss
DQPa
NC
E
NC
DQb
VSS
CE
Vss
NC
DQa
F
VDDQ
NC
VSS
OE
Vss
DQa
VDDQ
G
NC
DQb
BWb
NC
NC
NC
DQa
H DQb
NC
VSS
WE
Vss
DQa
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
DQb
VSS
CLK
Vss
NC
DQa
L _DQb
NC
NC
NC
BWa
DQa
NC
M
VDDQ
DQb
VSS
CKE
Vss
NC
VDDQ
N DQb
NC
VSS
A1*
Vss
DQa
NC
P
NC
DQPb VSS
A0*
Vss
NC
DQa
R
NC
A
MODE VDD
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U VDDQ
NC
NC
NC
NC
NC
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx (x=a,b)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
OE
ZZ
MODE
VDD
VSS
NC
DQa-DQb
DQPa-Pb
VDDQ
Output Enable
Power Sleep Mode
Burst Sequence Selection
Power Supply
Ground
No Connect
Data Inputs/Outputs
Parity Data I/O
Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. 00A
08/26/05