IS61LV25616L Datasheet, PDF (7/11 Pages) Integrated Silicon Solution, Inc – 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

IS61LV25616L
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
1
-10
-12
-15
Symbol Parameter
Min. Max. Min. Max. Min. Max. Unit
tWC
Write Cycle Time
tSCE
CE to Write End
10 —
12 —
15 —
ns
8—
8—
10 —
ns
2
tAW
Address Setup Time
8—
8—
10 —
ns
to Write End
tHA
Address Hold from Write End
0—
0—
0—
ns
3
tSA
Address Setup Time
0—
0—
0—
ns
tPWB
tPWE1
LB, UB Valid to End of Write
WE Pulse Width
8—
8—
8—
10 —
ns
8—
10 —
ns
4
tPWE2
WE Pulse Width (OE = LOW)
10 —
12 —
12 —
ns
tSD
Data Setup to Write End
tHD
Data Hold from Write End
6—
0—
6—
0—
7—
ns
0—
ns
5
tHZWE⁽²⁾ WE LOW to High-Z Output
—5
—6
—7
ns
tLZWE⁽²⁾
Notes:
WE HIGH to Low-Z Output
2—
2—
2—
ns
6
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
7
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
Shaded area product in development
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. B
06/28/02