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IS61WV12816EDBLL Datasheet, PDF (6/14 Pages) Integrated Silicon Solution, Inc – 128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC | |||
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IS61/64WV12816EDBLL
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
Output Load
Unit
(2.4V-3.6V)
0.4V to Vdd-0.3V
1V/ ns
Vdd/2
See Figures 1 and 2
AC TEST LOADS
OUTPUT
ZO = 50â¦
50â¦
1.5V
30 pF
Including
jig and
scope
Figure 1.
3.3V
319 â¦
OUTPUT
5 pF
Including
jig and
scope
Figure 2.
353 â¦
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -20
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
trc
Read Cycle Time
8â
10 â
20 â
ns
taa
Address Access Time
â8
â 10
â 20
ns
toha
Output Hold Time
2.0 â
2.0 â
2.5 â
ns
tace
CE Access Time
â8
â 10
â 20
ns
tdoe
OE Access Time
â 4.5
â 4.5
â8
ns
thzoe(2) OE to High-Z Output
â3
â4
08
ns
tlzoe(2)
OE to Low-Z Output
0â
0â
0â
ns
thzce(2
CE to High-Z Output
03
04
08
ns
tlzce(2)
CE to Low-Z Output
3â
3â
3â
ns
tba
LB, UB Access Time
â 5.5
â 6.5
â8
ns
thzb(2)
LB, UB to High-Z Output
03
03
08
ns
tlzb(2)
LB, UB to Low-Z Output
0â
0â
0â
ns
tpu
Power Up Time
0â
0â
0â
ns
tpd
Power Down Time
â8
â 10
â 20
ns
Notes:
1.â Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2.â Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage.
6
Integrated Silicon Solution, Inc. â www.issi.com
Rev. A
09/29/2011
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