IS61NLP25636A Datasheet, PDF (6/37 Pages) Integrated Silicon Solution, Inc – 256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A
ISSI ^®
165-PIN PBGA PACKAGE CONFIGURATION 512K x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A NC
A
CE ^{BWb NC} CE2 ^{CKE ADV}
A
A
A
B NC
A
CE2 _NC
BWa CLK
WE
OE
NC
A
NC
C NC
NC
VDDQ Vss
Vss _Vss
Vss
Vss VDDQ NC DQPa
D NC DQb VDDQ VDD
Vss Vss
Vss
VDD
VDDQ
NC
DQa
E NC DQb ^VDDQ VDD
Vss Vss
Vss
VDD _VDDQ
NC
DQa
F
NC
DQb ^VDDQ _VDD
Vss Vss
Vss
VDD
VDDQ
NC
DQa
G
NC
DQb
VDDQ _VDD
H NC NC
NC ^VDD
Vss Vss Vss
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
VDD
NC
NC
ZZ
J _DQb
NC
VDDQ _VDD
Vss
Vss
Vss
VDD _{VDDQ DQa NC}
K _{DQb NC VDDQ VDD}
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
L _{DQb NC VDDQ VDD}
Vss Vss
Vss
VDD
VDDQ
DQa ^NC
M DQb NC ^VDDQ VDD
Vss ^Vss
Vss
VDD _VDDQ
DQa
NC
N DQPb NC VDDQ Vss
NC
NC
NC
Vss _VDDQ
NC
NC
P NC ^NC
A
A
TDI
A1* TDO
A
A
A
NC
R MODE ^NC
A
A
TMS
A0*
TCK
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
WE
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
CLK
Synchronous Clock
CKE
Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a,b) Synchronous Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQx
DQPx
VDDQ
VSS
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/27/06