IS61LV3216 Datasheet, PDF (6/8 Pages) Integrated Silicon Solution, Inc – 32K x 16 LOW VOLTAGE CMOS STATIC RAM

IS61LV3216
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol Parameter
tWC Write Cycle Time
tSCE CE to Write End
tAW Address Setup Time
to Write End
tHA Address Hold from Write End
tSA Address Setup Time
tPWB LB, UB Valid to End of Write
tPWE WE Pulse Width
tSD Data Setup to Write End
tHD Data Hold from Write End
tHZWE⁽²⁾ WE LOW to High-Z Output
tLZWE⁽²⁾ WE HIGH to Low-Z Output
-10
Min. Max.
10 —
9—
9—
0—
0—
9—
7—
5—
0—
—5
1—
-12
Min. Max.
12 —
10 —
10 —
0—
0—
10 —
8—
6—
0—
—6
1—
-15
Min. Max.
15 —
11 —
11 —
0—
0—
11 —
10 —
7—
0—
—7
1—
-20
Min. Max. Unit
20 — ns
12 — ns
12 — ns
0 — ns
0 — ns
12 — ns
11 — ns
— 8 ns
0 — ns
— 8 ns
1 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be
in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01