IS61LV25616 Datasheet, PDF (6/11 Pages) Integrated Circuit Solution Inc – 256 X 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

IS61LV25616
ISSI ^®
AC WAVEFORMS
READ CYCLE NO. 1^(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
ADDRESS
DOUT
t RC
t AA
t OHA
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2^(1,3)
ADDRESS
OE
CE
LB, UB
tLZCE
DOUT
tLZB
HIGH-Z
tRC
tAA
tOHA
tDOE
tLZOE
tACE
tHZOE
tHZCE
tBA
tRC
tHZB
DATA VALID
VCC
Supply
Current
tPU
50%
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
tPD
ICC
50%
ISB
UB_CEDR2.eps
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00