IS43TR16256A Datasheet, PDF (53/81 Pages) Integrated Silicon Solution, Inc – 512Mx8, 256Mx16 4Gb DDR3 SDRAM

IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
8. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600
8.1 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result
in malfunction of the DDR3 SDRAM device.
8.1.1 Definition for tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is
calculated from rising edge to rising edge.
tCK(avg) = (
tCKj ) / N
Where N=200
8.1.2 Definition for tCK(abs)
tCK(abs) is defind as the absolute clock period, as measured from one rising edge to the next consecutive rising edge.
tCK(abs) is not subject to production test.
8.1.3 Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:
tCH(avg) = (
tCHj ) / (N x tCK(avg)
Where N=200
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:
tCL(avg) = (
tCLj ) / (N x tCK(avg)
Where N=200
8.1.4 Definition for note for tJIT(per), tJIT(per, Ick)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).
tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
8.1.5 Definition for tJIT(cc), tJIT(cc, Ick)
Integrated Silicon Solution, Inc. – www.issi.com –
53
Rev. 00A
11/14/2012