IS43TR16256A Datasheet, PDF (17/81 Pages) Integrated Silicon Solution, Inc – 512Mx8, 256Mx16 4Gb DDR3 SDRAM

IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
Memory Core
(all banks
precharged)
MR3[A2]
Multipurpose
Register pre-defined
data for read
DQ, DM, DQS, DQS#
Figure 2.3.5.1 MPR Block Diagram
To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1. Prior to
issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is
enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register.
The resulting operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled.
When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the
MPR disabled (MR3 bit A2 = 0).
Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of
RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR
enable mode. The RESET function is supported during MPR enable mode.
MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
MPR
MPR-Loc
0b
don’t care (0b or 1b)
1b
See Table 13
Function
Normal operation, no MPR transaction. All subsequent Reads will come from DRAM
array. All subsequent Write will go to DRAM array.
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
Integrated Silicon Solution, Inc. – www.issi.com –
17
Rev. 00A
11/14/2012