IS66WVD2M16ALL Datasheet, PDF (43/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD2M16ALL
Figure 28: Asynchronous WRITE
Address
ADQ0-
ADQ15
ADV#
CE#
t_AS
VALID
ADDRESS
t_AVS
t_AVH
VALID
ADDRESS
t_VP
t_AS
t_CVP
t_AW
t_VS
t_CW
t_DS
t_DH
VALID
DATA
UB#/LB#
WE#
HiZ
WAIT³#
t_BW
t_WP
NOTE2
HiZ
Notes:
1. The end of the WRITE cycle is controlled by CE#, UB#, LB#, or WE#, whichever de-asserts first.
2. WE# must not remain LOW longer than 4μs (tCEM) while the device is selected (CE# LOW).
3. During asynchronous WRITE cycles, WAIT will be High-Z while WE# is LOW or OE# is HIGH.
Rev.A | May 2011
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