IS66WVD2M16ALL Datasheet, PDF (33/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD2M16ALL
Table18 . Burst WRITE Cycle Timing Requirements
Symbol
Parameter
t_AS
t_CBPH
t_CEM
t_CLK
t_CSP
t_HD
t_KH/t_KL
t_KW
t_SP
t_T
t_WZ
Address and ADV# LOW Setup
Time
CE# High between Subsequent
Burst or Mixed-Mode Operations
Maximum CE# Pulse width
CLK Period
CE# Setup Time to Active CLK
Edge
Hold Time from Active CLK Edge
CLK HIGH or LOW Time
CLK to WAIT Valid
Setup time to Active CLK Edge
CLK Rise or Fall Time
CE# high to WAIT High-Z
-7010
Min Max
-7008
Min Max
0
0
5
6
4
4
9.62
12.5
3
4
2
2
3
4
7
9
3
3
1.6
1.8
7
7
Unit Note
ns
1
ns
2
us
2
ns
ns
ns
ns
ns
3
ns
ns
ns
4
Notes:
1. tAS required if tCSP > 20ns.
2. A refresh opportunity must be provided every tCEM by taking CE# HIGH.
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 16.
The High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
Table19 . Initialization and DPD Timing Requirements
Symbol
Parameter
-70
Unit
Min Max
t_DPD
Time from DPD entry to DPD exit
150
us
t_DPDX CE# LOW time to exit DPD
70
ns
t_PU
Initialization Period (required before normal operations)
150
us
Notes
Rev.A | May 2011
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