IS63LV1024 Datasheet, PDF (4/8 Pages) Integrated Silicon Solution, Inc – 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT

IS63LV1024
ISSI ^®
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
-8 ns
-10 ns
-12 ns
-15 ns
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
tRC Read Cycle Time
8
—
10
—
12
—
15
—
ns
tAA Address Access Time
—
8
—
10
—
12
—
15
ns
tOHA Output Hold Time
2
—
2
—
3
—
3
—
ns
tACE CE Access Time
—
8
—
10
—
12
—
15
ns
tDOE OE Access Time
—
4
—
5
—
6
—
7
ns
tLZOE⁽²⁾ OE to Low-Z Output
0
—
0
—
0
—
0
—
ns
tHZOE⁽²⁾ OE to High-Z Output
0
4
0
5
0
6
0
7
ns
tLZCE⁽²⁾ CE to Low-Z Output
3
—
3
—
3
—
3
—
ns
tHZCE⁽²⁾ CE to High-Z Output
0
4
0
5
0
6
0
7
ns
tPU CE to Power Up Time
0
—
0
—
0
—
0
—
ns
tPD CE to Power Down Time
—
8
—
10
—
12
—
15
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1
output loading specified in Figure 1.
2. Tested with the C2 load in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
ZOUT = 50 Ω
OUTPUT
50 Ω
VT = 1.5V
Figure 1
4
3.3V
317 Ω
OUTPUT
5 pF
Including
jig and
scope
Figure 2
351 Ω
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00