IS61QDB44M18A Datasheet, PDF (4/30 Pages) Integrated Silicon Solution, Inc – 2Mx36 and 4Mx18 configuration available

IS61QDB44M18A
IS61QDB42M36A
SRAM Features description
Block Diagram
36 (18)
D (Data-In)
Data
Register
19 (20)
Address
Address
Register
19 (20)
R#
W#
BWx#
4 (2)
Control
Logic
K
K#
C
C#
Doff#
Clock
Generator
72 (36) 72 (36)
Write
Driver
2M x 36
(4M x 18)
Memory Array
72 (36)
72 (36)
Output ^{144 (72)}
Register
Select Output Control
36 (18)
Q (Data-out)
2
CQ, CQ#
(Echo Clocks)
Note: Numerical values in parentheses refer to the x18 device configuration.
Read Operations
The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R# in active low state
at the rising edge of the K clock. R# can be activated every other cycle because two full cycles are required to
complete the burst of four in DDR mode. A second set of clocks, C and C#, are used to control the timing to the
outputs. A set of free-running echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs.
The echo clocks can be used as data capture clocks by the receiver device.
When the C and C# clocks are connected high, then the K and K# clocks assume the function of those clocks. In this
case, the data corresponding to the first address is clocked one and half cycles later by the rising edge of the K# clock.
The data corresponding to the second burst is clocked two cycles later by the following rising edge of the K clock. The
third data-out is clocked by the subsequent rising edge of the K# clock, and the fourth data-out is clocked by the
subsequent rising edge of the K clock.
A NOP operation (R# is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every other rising edge of the K clock whenever W# is low. The write address
is provided simultaneously. Again, the write always occurs in bursts of four.
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is
presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write
burst address follows next, registered by the rising edge of K#. The third data-in is clocked by the subsequent rising
edge of the K clock, and the fourth data-in is clocked by the subsequent rising edge of the K# clock.
Integrated Silicon Solution, Inc.- www.issi.com
4
Rev. B
08/21/2014