IS61QDB44M18A Datasheet, PDF (3/30 Pages) Integrated Silicon Solution, Inc – 2Mx36 and 4Mx18 configuration available

IS61QDB44M18A
IS61QDB42M36A
Ball Descriptions
Symbol
K, K#
C, C#
CQ, CQ#
Doff#
SA
D0 - Dn
Q0 - Qn
W#
R#
BWx#
VREF
VDD
VDDQ
Type
Input
Input
Output
Input
Input
Input
Output
Input
Input
Input
Input
reference
Power
Power
Description
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
These balls cannot remain VREF level.
Input clock for output data. C and C# are used to clock out the READ data. They can be used
together to deskew the flight times of various devices on the board back to the controller. See
application example for further details.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals run freely and
do not stop when Q tri-states.
DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock
time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz.
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. These inputs are ignored when device is deselected.
Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K
and K# during WRITE operations. See BALL CONFIGURATION figures for ball site location of
individual signals.
The x18 device uses D0~D17. D18~D35 should be treated as NC pin.
The x36 device uses D0~D35.
Synchronous data outputs: Output data is synchronized to the respective C and C#, or to the
respective K and K# if C and /C are tied to high. This bus operates in response to R# commands.
See BALL CONFIGURATION figures for ball site location of individual signals.
The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.
The x36 device uses Q0~Q35.
Synchronous write: When low, this input causes the address inputs to be registered and a WRITE
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.
Synchronous read: When low, this input causes the address inputs to be registered and a READ
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals are sampled on the same edge as the corresponding
data and must meet setup and hold times around the rising edges of K and #K for each of the two
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating
Conditions for range.
VSS
ZQ
TMS, TDI,
TCK
TDO
NC
Ground
Input
Input
Output
N/A
Ground of the device
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this
ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance
mode. This ball cannot be connected directly to VSS or left unconnected.
IEEE1149.1 input pins for JTAG.
IEEE1149.1 output pins for JTAG.
No connect: These signals should be left floating or connected to ground to improve package heat
dissipation.
Integrated Silicon Solution, Inc.- www.issi.com
3
Rev. B
08/21/2014