75V16F64GS16 Datasheet, PDF (37/50 Pages) Integrated Silicon Solution, Inc – 64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM STACKED MULTI-CHIP PACKAGE (MCP)

75V16F64GS16
PSRAM POWER DOWN PARAMETER
Parameter
CE2r Low Setup Time for Power down Entry
CE2r Low Setup Time after Power down Entry
CE1r High Hold Time Following CE2r High after Power down Exit
CE1r High Setup Time Following CE2r High after Power down Exit
Symbol
tCSP
tC2LP
tCHH
tCHS
ISSI ^®
Value
Min. Max.
Unit
10
—
ns
100
—
ns
350
—
µs
10
—
ns
PSRAM OTHER TIMING PARAMETERS
Parameter
Symbol
Value
Min. Max.
CE1r High to OE Invalid for Standby Entry
tCHOX
20
—
CE1r High to WE Invalid for Standby Entry⁽¹⁾
tCHWX
20
—
CE2r Low Hold Time after Power-up⁽²⁾
tC2LH
50
—
CE2r High Hold Time after Power-up⁽³⁾
tC2HL
50
—
CE1r High Hold Time Following CE2r High after Power-up⁽²⁾
tCHH
350
—
Input Transition Time⁽⁴⁾
tT
1
25
Notes:
1. Unintended data may be written into any address location if tCHWX is not satisfied.
2. Must satisfy tCHH (Min) after tC2LH (Min) .
3. Requires Power Down mode entry and exit after tC2HL.
4. Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns,
it may violate some timing parameters of AC specification.
Unit
ns
ns
µs
µs
µs
ns
PSRAM AC TEST CONDITIONS
Parameter
Input HIgh Level
Input Low Level
Input Timing Measurement Level
Input Transition Time
Symbol
VIH
VIL
VREF
tT
Conditon
VCCr = 2.7V to 3.1V
VCCr = 2.7V to 3.1V
VCCr = 2.7V to 3.1V
Between VIL and VIH
Value
Unit
2.3
V
0.4
V
1.3
V
5
ns
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
37
PRELIMINARY INFORMATION Rev. 00A
08/01/02