IS42S16100_08 Datasheet, PDF (36/81 Pages) Integrated Silicon Solution, Inc – 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

IS42S16100
Bank Active Command Interval
When the selected bank is precharged, the period trp
has elapsed and the bank has entered the idle state,
the bank can be activated by executing the active
command. If the other bank is in the idle state at that
time, the active command can be executed for that bank
after the period trrd has elapsed. At that point both
banks will be in the active state. When a bank active
command has been executed, a precharge command
must be executed for
that bank within the ACT to PRE command period (tras max).
Also note that a precharge command cannot be executed
for an active bank before tras (min) has elapsed.
After a bank active command has been executed and
the trcd period has elapsed, read write (including auto-
precharge) commands can be executed for that bank.
CLK
COMMAND
ACT 0
tRRD
BANK ACTIVE (BANK 0)
ACT 1
BANK ACTIVE (BANK 1)
CLK
COMMAND
ACT 0
tRCD
CAS latency = 3
BANK ACTIVE (BANK 0)
READ 0
BANK ACTIVE (BANK 0)
Clock Suspend
When the CKE pin is dropped from HIGH to LOW during a
read or write cycle, the IS42S16100 enters clock suspend
mode on the next CLK rising edge. This command reduces
the device power dissipation by stopping the device internal
clock. Clock suspend mode continues as long as the CKE
pin remains low. In this state, all inputs other than CKE
pin are invalid and no other commands can be executed.
Also, the device internal states are maintained. When the
CKE pin goes from LOW to HIGH clock suspend mode
is terminated on the next CLK rising edge and device
operation resumes.
The next command cannot be executed until the recovery
period (tcka) has elapsed.
Since this command differs from the self-refresh command
described previously in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tref). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.
CLK
CKE
COMMAND
READ 0
DQ
READ (BANK 0)
CAS latency = 2, burstlength = 4
36
DOUT 0
DOUT 1
CLOCK SUSPEND
DOUT 2 DOUT 3
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  D
01/28/08