IS42R86400D Datasheet, PDF (29/66 Pages) Integrated Silicon Solution, Inc – Internal bank for hiding row access/precharge

IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D
CHIP OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated
(see Activating Specific Row Within Specific Bank).
After opening a row (issuing an ACTIVE command), a READ
or WRITE command may be issued to that row, subject to
the trcd specification. Minimum trcd should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a trcd specification of 15ns with a
143 MHz clock (7ns period) results in 2.14 clocks, rounded
to 3. This is reflected in the following example, which cov-
ers any case where 2 < [trcd (MIN)/tck] ≤ 3. (The same
procedure is used to convert other specification limits from
time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by trc.
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defined by trrd.
ACTIVATING SPECIFIC ROW WITHIN SPE-
CIFIC BANK
CLK
HIGH
CKE
CS
RAS
CAS
WE
A0-A12
BA0, BA1
ROW ADDRESS
BANK ADDRESS
EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3
T0
T1
CLK
COMMAND ACTIVE
NOP
tRCD
T2
T3
T4
NOP
READ or
WRITE
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Integrated Silicon Solution, Inc. — www.issi.com
29
Rev. A
08/29/2012