IS42VS83200D Datasheet, PDF (24/61 Pages) Integrated Silicon Solution, Inc – Random column address every clock cycle

IS42VS83200D, IS42VS16160D
IS45VS83200D, IS45VS16160D
Register Definition
Mode Register
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODE REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
MODE REGISTER DEFINITION
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10, M11,
and M12 are reserved for future use.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation.Violating either of these
requirements will result in unspecified operation.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0 Address Bus (Ax)
Mode Register (Mx)
Reserved⁽¹⁾
Burst Length
M2 M1 M0
000
001
010
011
100
101
110
111
M3=0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3=1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
Type
0
Sequential
1 Interleaved
Latency Mode
M6 M5 M4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7
00
——
M6-M0
Defined
—
Mode
Standard Operation
All Other States Reserved
Write Burst Mode
M9
Mode
0
Programmed Burst Length
1
Single Location Access
1. To ensure compatibility with future devices,
should program BA1, BA0, A12, A11, A10 = "0"
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Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00A
04/21/09