IS42VS83200D Datasheet, PDF (1/61 Pages) Integrated Silicon Solution, Inc – Random column address every clock cycle

IS42VS83200D, IS42VS16160D
IS45VS83200D, IS45VS16160D
32Meg x 8, 16Meg x16 _{PRELIMINARY INFORMATION}
256-MBIT SYNCHRONOUS DRAM
MAY 2009
FEATURES
• Clock frequency: 133, 125MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single Power supply: 1.8V + 0.1V
• LVCMOS interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 16 ms (A2 grade) or
8K refresh cycles every 64 ms (Commercial,
Industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-pin TSOP-II (x8 and x16)
54-ball TF-BGA (x16 only)
• Operating Temperature Range:
Commercial (0^oC to +70^oC)
Industrial (-40^oC to +85^oC)
Automotive Grade, A1 (-40^oC to +85^oC)
Automotive Grade, A2 (-40^oC to +105^oC)
• Die Revision: D
OVERVIEW
ISSI's 256Mb Synchronous DRAMachieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized as follows.
IS42VS83200D IS42VS16160D
IS45VS83200D IS45VS16160D
8M x 8 x 4 Banks 4M x16x4 Banks
54-pin TSOPII 54-pin TSOPII
54-ball TF-BGA
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Timefrom Clock
CAS Latency = 3
CAS Latency = 2
-75
-8 Unit
7.5
8
ns
10
10
ns
133 125
Mhz
100 100
Mhz
5.4
6
ns
8
8
ns
ADDRESS TABLE
Parameter
32M x 8
Configuration
8M x 8 x 4
banks
Refresh Count
Com./Ind.
A1
A2
8K/64ms
8K/64ms
8K/16ms
Row Addresses
A0-A12
Column Addresses
A0-A9
Bank Address Pins
BA0, BA1
Auto Precharge Pins
A10/AP
16M x 16
4M x 16 x 4
banks
8K/64ms
8K/64ms
8K/16ms
A0-A12
A0-A8
BA0, BA1
A10/AP
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev.  00A
04/21/09