IS61LF25636A_10 Datasheet, PDF (23/32 Pages) Integrated Silicon Solution, Inc – 256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
TAP Electrical Characteristics Over the Operating Range^(1,2)
Symbol
Parameter
Test Conditions
Voh1
Output HIGH Voltage
Ioh = –2.0 mA
Voh2
Output HIGH Voltage
Ioh = –100 µA
Vol1
Output LOW Voltage
Iol = 2.0 mA
Vol2
Output LOW Voltage
Iol = 100 µA
Vih
Input HIGH Voltage
Vil
Input LOW Voltage
Iolt = 2mA
Ix
Input Load Current
Vss ≤ V I ≤ Vddq
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: Vih (AC) ≤ Vdd +1.5V for t ≤ ttcyc/2,
Undershoot: Vil (AC) ≤ 0.5V for t ≤ ttcyc/2,
Power-up: Vih < 2.6V and Vdd < 2.4V and Vddq < 1.4V for t < 200 ms.
Min.
1.7
2.1
—
—
1.7
–0.3
–5
Max.
—
—
0.7
0.2
Vdd +0.3
0.7
5
Units
V
V
V
V
V
V
mA
TAP AC ELECTRICAL CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol Parameter
Min.
Max.
ttcyc TCK Clock cycle time
100
—
ftf
TCK Clock frequency
—
10
tth
TCK Clock HIGH
40
—
ttl
TCK Clock LOW
40
—
ttmss TMS setup to TCK Clock Rise
10
—
ttdis
TDI setup to TCK Clock Rise
10
—
tcs
Capture setup to TCK Rise
10
—
ttmsh TMS hold after TCK Clock Rise
10
—
ttdih
TDI Hold after Clock Rise
10
—
tch
Capture hold after Clock Rise
10
—
ttdov TCK LOW to TDO valid
—
20
ttdox TCK LOW to TDO invalid
0
—
Notes:
1. Both tcs and tch refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tr/tf = 1 ns.
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Integrated Silicon Solution, Inc.
23
Rev. H
07/22/2010