IS66WVE1M16BLL Datasheet, PDF (22/30 Pages) Integrated Silicon Solution, Inc – 3.0V Core Async/Page PSRAM

IS66WVE1M16BLL
Table10 . Load Configuration Register Timing Requirements
Symb
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Parameter
t_AS
t_AW
t_CDZZ
t_CW
t_WC
t_WP
t_WR
t_ZZWE
Address setup time
Address valid to end of write
Chip deselect to ZZ# LOW
Chip enable to end of write
Write cycle time
Write pulse width
Write recovery time
ZZ# LOW to WE# LOW
-55
Min Max
0
55
5
55
55
46
0
10 500
-70
Unit
Min Max
0
ns
70
ns
5
ns
70
ns
70
ns
46
ns
0
ns
10
500 ns
Note
Table11 . DPD Timing Requirements
Symbol
Parameter
t_CDZZ
t_R
t_ZZ( MIN)
Chip deselect to ZZ# LOW
Deep Power-down recovery
Minimum ZZ# pulse width
-55/-70
Unit
Min
Max
5
ns
150
us
10
us
Notes
Table12 . Initialization Timing Requirements
Symbol
Parameter
-55/-70
Unit
Min Max
t_PU
Initialization Period (required before normal operations)
150
us
Notes
Rev. A | Feb. 2012
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