IS66WVE1M16BLL Datasheet, PDF (20/30 Pages) Integrated Silicon Solution, Inc – 3.0V Core Async/Page PSRAM

IS66WVE1M16BLL
AC Characteristics
Table 8 . Asynchronous READ Cycle Timing Requirements
Sym
bol
Parameter
t_AA Address Acess Time
t_APA Page access Time
t_BA LB# /UB# access Time
t_BHZ
LB#/UB# disable to High-Z
output
t_BLZ
LB#/UB# enable to Low-Z
output
t_CEM Maximum CE# pulse width
t_CO Chip select access time
t_HZ Chip disable to High-Z output
t_LZ Chip enable to Low-Z output
t_OE Output enable to valid output
t_OH
Output hold from address
change
t_OHZ Output disable to High-Z output
t_OLZ Output enable to Low-Z output
t_PC Page cycle time
t_RC Read cycle time
-55
Min
Max
55
20
55
8
10
8
55
8
10
20
5
8
3
20
55
-70
Min
Max
70
20
70
8
Unit Notes
ns
ns
ns
ns
1
10
ns
2
8
us
3
70
ns
8
ns
1
10
ns
2
20
ns
5
ns
8
ns
1
3
ns
2
20
ns
70
ns
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The High-Z timings
measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The Low-Z timings
measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or VOL.
3. Page mode enable only.
Rev. A | Feb. 2012
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