IS61QDPB44M18A Datasheet, PDF (21/33 Pages) Integrated Silicon Solution, Inc – 2Mx36 and 4Mx18 configuration available

IS61QDPB44M18A/A1/A2
IS61QDPB42M36A/A1/A2
Write and NOP Timing Diagram
Write
1
tKHKH
2
Write
3
4
K Clock
tKHKL tKLKH
tKHKH
K# Clock
NOP
NOP
NOP
5
6
7
8
9
Address
(SA)
A1
tAVKH tKHAX
A2
W#
tIVKH tKHIX
tIVKH2 tKHIX2
BWx#
B1-0 B1-1 B1-2 B1-3 B2-0 B2-1 B2-2 B2-3
tDVKH
tKHDX
Data-In
(D)
D1-0 D1-1 D1-2 D1-3 D2-0 D2-1 D2-2 D2-3
Undefined
Don’t Care
Notes:
1. D1-0 , D1-1, D1-2, and D1-3 refer to the output from address A1, Internal burst counter will assign them separately.
2. B1-0 refers to all BWx# byte controls for D1-0. B1-1, B1-2, and B1-3 refer to all BWx# byte controls for D1-1, D1-2, and D1-3 respectively.
3. B2-0 refers to all BWx# byte controls for D2-0. B2-1, B2-2, and B2-3 refer to all BWx# byte controls for D2-1, D2-2, and D2-3 respectively.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. E
21
07/07/2014