IS61QDPB44M18A Datasheet, PDF (13/33 Pages) Integrated Silicon Solution, Inc – 2Mx36 and 4Mx18 configuration available

IS61QDPB44M18A/A1/A2
IS61QDPB42M36A/A1/A2
x36 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
K
(t+2.0)
K#
(t+2.5)
K
(t+3.0)
K#
(t+3.5)
BW₀# BW₁# BW₂# BW₃#
D_B
D_B+1
D_B+2
D_B+3
Write Byte 0
L→H
L
H
H
H
D0-8 (t+2.0)
Write Byte 1
Write Byte 2
Write Byte 3
Write All Bytes
L→H
L→H
L→H
L→H
H
L
H
H D9-17 (t+2.0)
H
H
L
H
H
H
H
L
D18-26
(t+2.0)
D27-35
(t+2.0)
L
L
L
L D0-35 (t+2.0)
Abort Write
L→H
H
H
H
H
Don't Care
Write Byte 0
L→H
L
H
H
H
D0-8 (t+2.5)
Write Byte 1
Write Byte 2
Write Byte 3
Write All Bytes
L→H
L→H
L→H
L→H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
L
L
D9-17 (t+2.5)
D18-26
(t+2.5)
D27-35
(t+2.5)
D0-35 (t+2.5)
Abort Write
L→H
H
H
H
H
Don't Care
Write Byte 0
L→H
L
H
H
H
D0-8 (t+3.0)
Write Byte 1
Write Byte 2
Write Byte 3
Write All Bytes
L→H
L→H
L→H
L→H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
L
L
D9-17 (t+3.0)
D18-26
(t+3.0)
D27-35
(t+3.0)
D0-35 (t+3.0)
Abort Write
L→H
H
H
H
H
Don't Care
Write Byte 0
L→H
L
H
H
H
D0-8 (t+3.5)
Write Byte 1
Write Byte 2
Write Byte 3
Write All Bytes
L→H
H
L
H
H
L→H
H
H
L
H
L→H
H
H
H
L
L→H
L
L
L
L
D9-17 (t+3.5)
D18-26
(t+3.5)
D27-35
(t+3.5)
D0-35 (t+3.5)
Abort Write
L→H
H
H
H
H
Don't Care
Notes:
1. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. E
13
07/07/2014