IS61WV6416EEBLL Datasheet, PDF (2/15 Pages) Integrated Silicon Solution, Inc – 64K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC

IS61/64WV6416EEBLL
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read

Write

WE CE OE LB UB
XHXXX
HLHXX
X
L
X
H
H
H
L
L
L
H
H
L
L
H
L
H
L
L
L
L
L
L
X
L
H
L
L
X
H
L
L
L
X
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Dout
High-Z
Dout
Dout
Din
High-Z
Din
High-Z
Din
Din
Vdd Current
Isb1, Isb2
Icc
Icc
Icc
PIN CONFIGURATIONS
44-Pin TSOP-II
A15 1
A14 2
A13 3
A12 4
A11 5
CE 6
I/O0 7
I/O1 8
I/O2 9
I/O3 10
VDD 11
GND 12
I/O4 13
I/O5 14
I/O6 15
I/O7 16
WE 17
A10 18
A9 19
A8 20
A7 21
NC 22
44 A0
43 A1
42 A2
41 OE
40 UB
39 LB
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 GND
33 VDD
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 NC
27 A3
26 A4
25 A5
24 A6
23 NC
PIN DESCRIPTIONS
A0-A15
Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC No Connection
Vdd Power
GND
Ground
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
10/10/2012