IS61QDB41M18A Datasheet, PDF (19/30 Pages) Integrated Silicon Solution, Inc – 512Kx36 and 1Mx18 configuration available

IS61QDB41M18A
IS61QDB451236A
READ, WRITE, AND NOP TIMING DIAGRAM
1
2
3
4
5
6
7
READ
WRITE
tKHKH
READ
WRITE
NOP
K Clock
K# Clock
tKHKL
tKHK#H
tKLKH
tAVKH tKHAX
Address
(SA)
A1
A2
A3
A4
tIVKH tKHIX
R#
tIVKH tKHIX
W#
BW_x#
Data-In
(D)
Data-Out
(Q)
C Clock
C# Clock
tKHCH
tKHKH
tKHKL tKLKH
tKHK#H
tIVKH2
tKHDX2
B2-1 B2-2 B2-3 B2-4 B4-1 B4-2 B4-3 B4-4
tDVKH
tKHDX
D2-1 D2-2 D2-3 D2-4 D4-1 D4-2 D4-3 D4-4
tCHQX1
Q1-1
tCHQV
Q1-2
Q1-3
Q1-4
Q3-1
Q3-2
Q3-3
Q3-4
tCHQZ
tCHQX
tCHCQX
CQ Clock
CQ# Clock
tCQHQV
tCQHQX
tCHCQV
Undefined
Don’t Care
Notes:
1. If address A3 = A2, data Q3-1 = D2-1, data Q3-2 = D2-2, data Q3-3 = D2-3, data Q3-4 = D2-4. Write data is forwarded immediately as read
results.
2. B2-1 refers to all BWx# byte controls for D2-1. B2-2, B2-3, and B2-4 refer to all BWx# byte controls for D2-2, D2-3, and D2-4 respectively.
3. B4-1 refers to all BWx# byte controls for D4-1. B4-2, B4-3, and B4-4 refer to all BWx# byte controls for D4-2, D4-3, and D4-4 respectively.
4. Outputs are disabled one cycle after a NOP.
Integrated Silicon Solution, Inc.- www.issi.com
19
Rev. B
10/02/2014