IS61QDB41M18A Datasheet, PDF (12/30 Pages) Integrated Silicon Solution, Inc – 512Kx36 and 1Mx18 configuration available

IS61QDB41M18A
IS61QDB451236A
x36 WRITE TRUTH TABLE
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
K (t+1.0) K# (t+1.5) K (t+2.0) K# (t+2.5) BW₀# BW₁# BW₂# BW₃#
Write Byte 0
L→H
L
H
H
H
Write Byte 1
L→H
H
L
H
H
Write Byte 2
L→H
H
H
L
H
Write Byte 3
L→H
H
H
H
L
Write All Bytes
L→H
L
L
L
L
D_B
D0-8
(t+2.0)
D9-17
(t+2.0)
D18-26
(t+2.0)
D27-35
(t+2.0)
D0-35
(t+2.0)
Abort Write
L→H
H
H
H
H Don't Care
Write Byte 0
L→H
L
H
H
H
Write Byte 1
L→H
H
L
H
H
Write Byte 2
L→H
H
H
L
H
Write Byte 3
L→H
H
H
H
L
Write All Bytes
L→H
L
L
L
L
Abort Write
L→H
H
H
H
H
Write Byte 0
L→H
L
H
H
H
Write Byte 1
L→H
H
L
H
H
Write Byte 2
L→H
H
H
L
H
Write Byte 3
L→H
H
H
H
L
Write All Bytes
L→H
L
L
L
L
Abort Write
L→H
H
H
H
H
Write Byte 0
L→H
L
H
H
H
Write Byte 1
L→H
H
L
H
H
Write Byte 2
L→H
H
H
L
H
Write Byte 3
L→H
H
H
H
L
Write All Bytes
L→H
L
L
L
L
Abort Write
L→H
H
H
H
H
D_B+1
D0-8
(t+2.5)
D9-17
(t+2.5)
D18-26
(t+2.5)
D27-35
(t+2.5)
D0-35
(t+2.5)
Don't
Care
D_B+2
D_B+3
D0-8
(t+3.0)
D9-17
(t+3.0)
D18-26
(t+3.0)
D27-35
(t+3.0)
D0-35
(t+3.0)
Don't Care
D0-8
(t+3.5)
D9-17
(t+3.5)
D18-26
(t+3.5)
D27-35
(t+3.5)
D0-35
(t+3.5)
Don't Care
Notes:
1. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
Integrated Silicon Solution, Inc.- www.issi.com
12
Rev. B
10/02/2014