IS43TR16512A Datasheet, PDF (19/80 Pages) Integrated Silicon Solution, Inc – Programmable CAS Latency

IS43/46TR16512A, IS43/46TR16512AL,
2.4 DDR3 SDRAM Command Description and Operation
2.4.1 Command Truth Table
[BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop, X=Don’t Care, V=Valid]
Function
Abbrev.
CKE
Previous Current
Cycle
Cycle
CS# RAS#
CAS#
WE#
BA0-
BA2
A11,
A13
A14
A12/
BC#
A10
/AP
A0
-
A9
Notes
Mode Register Set
MRS
H
H
L
L
L
L BA
OP Code
Refresh
REF
H
H
L
L
L
H
V
V
VVV
Self Refresh Entry
SRE
H
L
L
L
L
H
V
V
V V V 7,9,12
Self Refresh Exit
SRX
L
H
H
X
L
H
X
X
X
X
X X X 7,8,9,
H
H
V
V
VVV
12
Single Bank Precharge
PRE
H
H
L
L
H
L
BA
V
V
L
V
Precharge all Banks
PREA
H
H
L
L
H
L
V
V
V
H
V
Bank Activate
ACT
H
H
L
L
H
H
BA
Row Address(RA)
Write (Fixed BL8 or BC4)
WR
H
H
L
H
L
L
BA RFU V
L CA
Write (BC4, on the Fly) WRS4
H
H
L
H
L
L
BA RFU L
L CA
Write (BL8, on the Fly) WRS8
H
H
L
H
L
L
BA RFU H
L CA
Write with Auto Precharge
(Fixed BL8 or BC4)
WRA
H
H
L
H
L
L
BA RFU V
H CA
Write with Auto Precharge
(BC4, on the Fly)
WRAS4
H
H
L
H
L
L
BA RFU L
H CA
Write with Auto Precharge
(BL8, on the Fly)
WRAS8
H
H
L
H
L
L
BA RFU H
H CA
Read (Fixed BL8 or BC4)
RD
H
H
L
H
L
H
BA RFU V
L CA
Read (BC4, on the Fly) RDS4
H
H
L
H
L
H
BA RFU L
L CA
Read (BL8, on the Fly)
RDS8
H
H
L
H
L
H
BA RFU H
L CA
Read with Auto Precharge
(Fixed BL8 or BC4)
RDA
H
H
L
H
L
H
BA RFU V
H CA
Read with Auto Precharge
(BC4, on the Fly)
RDAS4
H
H
L
H
L
H
BA RFU L
H CA
Read with Auto Precharge
(BL8, on the Fly)
RDAS8
H
H
L
H
L
H
BA RFU H
H CA
No Operation
NOP
H
H
L
H
H
H
V
V
V
V
V
10
Device Deselected
DES
H
H
H
X
X
X
X
X
X
X
X
11
Power Down Entry
PDE
H
L
L
H
H
X
H
X
H
X
V
X
V
X
V
X
V
X
V
X
6,12
Power Down Exit
PDX
L
H
L
H
H
X
H
X
H
X
V
X
V
X
V
X
V
X
V
X
6,12
ZQ Calibration Long
ZQCL
H
H
L
H
H
L
X
X
X
H
X
ZQ Calibration Short
ZQCS
H
H
L
H
H
L
X
X
X
L
X
Notes:
1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock. The MSB of BA, RA and CA
are device density and configuration dependant.
2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function.
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.
6. The Power Down Mode does not perform any refresh operation.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
8. Self Refresh Exit is asynchronous.
9. VREF(Both VrefDQ and VrefCA) must be maintained during Self Refresh operation. VrefDQ supply may be turned OFF and VREFDQ may take any
value between VSS and VDD during Self Refresh operation, provided that VrefDQ is valid and stable prior to CKE going back High and that first
Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh.
10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose of the No Operation command
(NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A No Operation command will not terminate a
pervious operation that is still executing, such as a burst read or write cycle.
11. The Deselect command performs the same function as No Operation command.
12. Refer to the CKE Truth Table for more detail with CKE transition.
Integrated Silicon Solution, Inc. – www.issi.com –
19
Rev. A
08/13/2014