IS61WV20488ALL Datasheet, PDF (12/20 Pages) Integrated Silicon Solution, Inc – 2M x 8 HIGH-SPEED CMOS STATIC RAM

IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol
Parameter
-20 ns
Min. Max.
Unit
tWC
Write Cycle Time
20 —
ns
tSCE
CE to Write End
12 —
ns
tAW
Address Setup Time
to Write End
12 —
ns
tHA
Address Hold from Write End
0—
ns
tSA
Address Setup Time
0—
ns
tPWE1
WE Pulse Width (OE = HIGH)
12 —
ns
tPWE2
WE Pulse Width (OE = LOW)
17 —
ns
tSD
Data Setup to Write End
9—
ns
tHD
Data Hold from Write End
0—
ns
tHZWE⁽³⁾
WE LOW to High-Z Output
—9
ns
tLZWE⁽³⁾
WE HIGH to Low-Z Output
3—
ns
Notes:
1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V,
input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input
Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
ISSI ^®
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
01/09/06