IS61WV102416ALL-20TLI Datasheet, PDF (12/20 Pages) Integrated Silicon Solution, Inc – 1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

IS61WV102416ALL
IS61WV102416BLL
IS64WV102416BLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
-8
-10
Symbol Parameter Min. Max. Min. Max. Unit
twc
Write Cycle Time
8
—
10 —
ns
tsce
CE to Write End
6.5 —
8
—
ns
taw
Address Setup Time
to Write End
6.5 —
8
—
ns
tha
Address Hold from Write End
0
—
0
—
ns
tsa
Address Setup Time
0
—
0
—
ns
tpwb
LB, UB Valid to End of Write
6.5 —
8
—
ns
tpwe1
WE Pulse Width
6.5 —
8
—
ns
tpwe2
WE Pulse Width(OE = LOW)
8.0 —
10 —
ns
tsd
Data Setup to Write End
5
—
6
—
ns
thd
Data Hold from Write End
0
—
0
—
­ns
thzwe⁽²⁾ WE LOW to High-Z Output
— 3.5
—
5
ns
tlzwe⁽²⁾ WE HIGH to Low-Z Output
2
—
2
—
ns
Notes:
1.  Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW.All signals must be in valid states to initi-
ate a Write, but any one can go inactive to terminate the Write.The Data Input Setup and Hold timing are referenced to the rising
or falling edge of the signal that terminates the write. Shaded area product in development
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.  F
05/09/12