IS61NF25618-8.5TQ Datasheet, PDF (12/20 Pages) Integrated Silicon Solution, Inc – 128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM

IS61NF12832 IS61NF12836 IS61NF25618
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI ^®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
-8.5
Min. Max.
-9
Min. Max.
fmax
Clock Frequency
— 100
— 83
tKC
Cycle Time
10 —
12 —
tKH
Clock High Time
3—
3—
tKL
Clock Low Time
3—
3—
tKQ
Clock Access Time
— 8.5
—9
tKQX⁽²⁾ Clock High to Output Invalid
3—
3—
tKQLZ^(2,3) Clock High to Output Low-Z
2.5 —
2.5 —
tKQHZ^(2,3) Clock High to Output High-Z
—5
—5
tOEQ
Output Enable to Output Valid
— 3.5
— 3.5
tOELZ^(2,3) Output Enable to Output Low-Z
0—
0—
tOEHZ^(2,3) Output Disable to Output High-Z
— 3.5
— 3.5
tAS
Address Setup Time
2—
2—
tWS
Read/Write Setup Time
2—
2—
tCES
Chip Enable Setup Time
2—
2—
tSE
Clock Enable Setup Time
2—
2—
tAVS
Address Advance Setup Time
2—
2—
tDS
Data Setup Time
2—
2—
tAH
Address Hold Time
0.5 —
0.5 —
tHE
Clock EnableHold Time
0.5 —
0.5 —
tWH
Write Hold Time
0.5 —
0.5 —
tCEH
Chip Enable Hold Time
0.5 —
0.5 —
tADVH
Address Advance Hold Time
0.5 —
0.5 —
tDH
Data Hold Time
0.5 —
0.5 —
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
-10
Min. Max.
— 83
12 —
3—
3—
— 10
3—
2.5 —
—6
— 3.5
0—
—4
2—
2—
2—
2—
2—
2—
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11/11/02