IS61WV10248ALL Datasheet, PDF (11/20 Pages) Integrated Silicon Solution, Inc – 1M x 8 HIGH-SPEED CMOS STATIC RAM

IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol Parameter
-8
Min. Max.
-10
Min. Max.
Unit
tWC
Write Cycle Time
8
—
10
—
ns
tSCE
CE to Write End
6.5 —
8
—
ns
tAW
Address Setup Time
to Write End
6.5 —
8
—
ns
tHA
Address Hold from Write End
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
ns
tPWE1
WE Pulse Width (OE = HIGH)
6.5 —
8
—
ns
tPWE2
WE Pulse Width (OE = LOW)
8.0 —
10
—
ns
tSD
Data Setup to Write End
5
—
6
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tHZWE⁽²⁾ WELOWtoHigh-ZOutput
— 3.5
—
5
ns
tLZWE⁽²⁾ WEHIGHtoLow-ZOutput
2
—
2
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write. Shaded area product in development
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. B
06/03/08