IS62WV2568EALL Datasheet, PDF (10/16 Pages) Integrated Silicon Solution, Inc – Three state outputs

IS62/65WV2568EALL
IS62/65WV2568EBLL
WRITE CYCLE NO. 1 (
ADDRESS
CS1#
CS2
WE#
DOUT
DIN
CONTROLLED,
= HIGH OR LOW)
tWC
tHA
tAW
tPWE
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA IN VALID
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if
Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 2 (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
tWC
ADDRESS
goes high before
OE#
CS1#
CS2
WE#
tSCS1
tHA
tSCS2
tAW
tPWE
DOUT
DIN
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA -IN VALID
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if
Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
goes high before
Integrated Silicon Solution, Inc.- www.issi.com
10
Rev. 0A
09/26/2014