IS62WV10248DALL Datasheet, PDF (10/15 Pages) Integrated Silicon Solution, Inc – TTL compatible interface levels

IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol Parameter
twc
Write Cycle Time
tscs1/tscs2 CS1/CS2 to Write End
taw
Address Setup Time to Write End
tha
Address Hold from Write End
tsa
Address Setup Time
tpwe⁽⁴⁾
WE Pulse Width
tsd
Data Setup to Write End
thd
Data Hold from Write End
thzwe⁽³⁾ WE LOW to High-Z Output
tlzwe⁽³⁾ WE HIGH to Low-Z Output
45ns
Min. Max.
45 —
35 —
35 —
0 —
0 —
35 —
20 —
0 —
— 20
5 —
55 ns
Min. Max.
55 —
45 —
45 —
0 —
0 —
40 —
25 —
0 —
— 20
5 —
70 ns
Min. Max.
70 —
60 —
60 —
0 —
0 —
50 —
30 —
0 —
— 30
5 —
Unit
ns
ns
ns
ns
ns
ns
ns
­ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of0.4 to
Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH, and WE LOW. All signals must be in valid states to initiate a Write, but any one can
go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. tpwe > thzwe + tsd when OE is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
ADDRESS
CS1
CS2
WE
DOUT
DIN
tWC
tSCS1
tHA
tSCS2
tAW
tPWE
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.  A
05/11/09