IS61QDP2B42M18A Datasheet, PDF (10/33 Pages) Integrated Silicon Solution, Inc – 1Mx36 and 2Mx18 configuration available

IS61QDP2B42M18A/A1/A2
IS61QDP2B41M36A/A1/A2
State Diagram
Power-Up
Read NOP
Read# Write#
Write NOP
Read#
D count = 2
Read
Load New Read
Address
D count = 0
Always
Read
D count = 2
DDR Read
D count =
D count +1
Read
D count = 1
Always
Increment Read
Address
Write
Load New Write
Address
D count = 0
Always
Write
D count = 2
DDR Write
D count =
D count +1
Write
D count = 1
Always
Increment Write
Address
Write#
D count = 2
Notes:
1. Internal burst counter is fixed as four-bit linear; that is when first address is A0+0, next internal burst addresses are A0+1, A0+2, and A0+3
2. Read refers to read active status with R# = LOW. Read# refers to read inactive status with R# = HIGH.
3. Write refers to write active status with W# = LOW. Write# refers to write inactive status with W# = HIGH.
4. The read and write state machines can be active simultaneously.
5. State machine control timing sequence is controlled by K.
Integrated Silicon Solution, Inc.- www.issi.com
10
Rev. B
12/15/2014