IS62WV6416DALL Datasheet, PDF (1/15 Pages) Integrated Silicon Solution, Inc – High-speed access time: 35ns, 45ns, 55ns

IS62WV6416DALL/DBLL
IS65WV6416DALL/DBLL
64K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
OCTOBER 2009
FEATURES
• High-speed access time: 35ns, 45ns, 55ns
• CMOS low power operation:
15 mW (typical) operating
1.5 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
1.65V--2.2V Vdd (62WV6416DALL)
2.3V--3.6V Vdd (65WV6416DBLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and automotive temperature support
• 2CS Option Available
• Lead-free available
DESCRIPTION
The ISSI IS62/65WV6416DALL and IS62/65WV6416DBLL
arehigh-speed, 1M bit static RAMs organized as 64K words
by 16 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is low
(deselected) or when CS1 is low, CS2 is high and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS62/65WV6416DALL and IS62/65WV6416DBLL are
packaged in the JEDEC standard 48-pin mini BGA (6mm
x 8mm) and 44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CS2
CS1
OE
WE
UB
LB
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
64K x 16
MEMORY ARRAY
COLUMN I/O
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev.  A
09/29/09