IS61VPS102436A Datasheet, PDF (1/21 Pages) Integrated Silicon Solution, Inc – 1Mb x 36, 2Mb x 18 36Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

IS61VPS102436A IS61LPS102436A
IS61VPS204818A IS61LPS204818A
1Mb x 36, 2Mb x 18
36Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
MARCH 2008
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP and 165-ball PBGA
packages
• Lead-free available
DESCRIPTION
The ISSI IS61LPS/VPS102436A and IS61LPS/VPS
204818A are high-speed, low-power synchronous static
RAMs designed to provide burstable, high-performance memory
for communication and networking applications. The
IS61LPS/VPS102436A is organized as 1,048,476 words
by 36 bits. The IS61LPS/VPS204818A is organized as
2M-word by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
200
166
Units
3.1
3.5
ns
5
6
ns
200
166
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc.
1
Rev. B
03/27/08