IS45S81600E Datasheet, PDF (1/61 Pages) Integrated Silicon Solution, Inc – 16M x 8, 8M x16 128Mb SYNCHRONOUS DRAM

IS45S81600E
IS45S16800E
16M x 8, 8M x16 _{FEBRUARY 2009}
128Mb SYNCHRONOUS DRAM
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply

IS45S81600E
Vdd Vddq
3.3V 3.3V
IS45S16800E
3.3V 3.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 4096 refresh cycles every 16 ms (A2 grade) or
64 ms (A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Automotive Temperature Range:
Option A1: -40^oC to +85^oC
Option A2: -40^oC to +105^oC
OVERVIEW
ISSI's 128Mb Synchronous DRAMachieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 128Mb SDRAM is organized as follows.
IS45S81600E IS45S16800E
4M x8 x4 Banks 2M x16 x4 Banks
54-pin TSOPII 54-pin TSOPII
54-ball BGA

KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Timefrom Clock
CAS Latency = 3
CAS Latency = 2
-6 -7 Unit
67
ns
10 10
ns
166 143
Mhz
100 100
Mhz
5.4 5.4
ns
6.5 6.5
ns
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. A
02/19/09