IRFB3006GPBF Datasheet, PDF (7/8 Pages) International Rectifier –
High Efficiency Synchronous Rectification in SMPS

IRFB3006GPbF
+
‚
-

R_G
D.U.T
+
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
ƒ
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance
Current Transformer
-^„ +
D.U.T. I_SD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V_DS Waveform _{Diode Recovery}
dv/dt
• dv/dt controlled by R_G
• Driver same type as D.U.T.
V_DD
+
• I_SD controlled by Duty Factor "D"
-
• D.U.T. - Device Under Test
Re-Applied
Voltage
Body Diode
I_In_nd_du_uc_ct_to_or_{r C}C_uu_rr_ere_nn_t t
Forward Drop
Ripple ≤ 5%
* V_GS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET^® Power MOSFETs
* V_GS=10V
V_DD
I_SD
V_(BR)DSS
15V
tp
VDS
L
DRIVER
RG
2V0GVS
tp
D.U.T
I_AS
0.01Ω
+
- ^VDD
A
Fig 22a. Unclamped Inductive Test Circuit
R_D
V_DS
V_GS
R_G
D.U.T.
+
-
V_DD
V1_G⁰_S^V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 23a. Switching Time Test Circuit
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
+
D.U.T. -V^DS
V_GS
3mA
I_G
I_D
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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I_AS
Fig 22b. Unclamped Inductive Waveforms
V_DS
90%
10%
V_GS
t_d(on) t_r
t_d(off) t_f
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2 Qgd
Qgodr
Fig 24b. Gate Charge Waveform
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