T0247 Datasheet, PDF (28/35 Pages) International Rectifier – Fit Rate / Equivalent Device Hours

POWER CYCLING (P/C) Unbiased
Test circuit
Conditions
Bias
Set to give ∆ T = 100°C
Temperature
Tj = ∆ 100°C
D
DC
Duration
10000 Cycles
BIAS
Test points
2500, 5000, 7500, 10000 Nominal
Input
Bias
D = Diode for CoPack devices only
Purpose
The purpose of Power Cycling is to simulate the thermal and current pulsing
stresses which devices will encounter in actual circuit applications when either the
equipment is turned on and off or power is applied to the device in short bursts
interspersed with quiescent, low power periods. The simulation is achieved by the
on/off application of power to each device while they are in the active linear
region.
Failure Modes
The primary failure mode for power cycling is a thermal fatigue of the
silicon/metal interfaces and metal/metal interfaces. The fatigue, due to the
thermomechanical stresses from the heating and cooling, will cause electrical or
thermal performance or degrade.
If the degradation occurs at the header/die interface, then the thermal impedance
Rθ_JC, will begin to increase well before any electrical effect is seen. If the
degradation occurs at the wire bond/die interface or the wire bond/post interface,
then on resistance, V_CE(on), will slowly increase or become unstable with time.
The thermal impedance, when measured during this time may appear to
decrease or change erratically.
The mechanical stresses from the application of power can also propagate
fractures in the silicon when the die is thermally mismatched to the solder/heat
sink system. These fractures will manifest themselves in the form of shorted
gates or degraded breakdown characteristics (V_(BR)CES).
Sensitive Parameters
I_CES, V_(BR)CES,Rθ_JC, V_CE(on)
IGBT / CoPack
Quarterly Reliability Report
Page 28 of 35