IP2003APBF Datasheet, PDF (2/10 Pages) International Rectifier – Synchronous Buck Multiphase Optimized LGA Power Block Intergrated Power Semiconductors,Drivers&Passives

iP2003APbF
All specifications @25°C (unless otherwise specified)
Absolute Maximum Ratings:
Parameter
Symbol Min
V_IN to PGND
V_IN
-
V_DD to PGND
V_DD
-
PWM to PGND
PWM
-0.3
Enable to PGND
ENABLE -0.3
Output RMS Current
I_OUT
-
Typ Max Units
Conditions
-
16
V
-
6.0
V
- V_DD +0.3 V ^{Not to exceed 6.0V}
- V_DD +0.3 V ^{Not to exceed 6.0V}
-
40
A ^{Measured at V}SW
Recommended Operating Conditions:
Parameter
Symbol Min Typ Max Units
Supply Voltage
V_DD
4.6
5.0
5.5
V
Input Voltage
V_IN
3.0
-
13.2
V
Output Voltage
V_OUT
0.8
-
3.3
V
Output Current
I_OUT
-
-
40
A
Operating Frequency
fsw
300
-
1000 kHz
Operating Duty Cycle
D
-
-
85
%
Block Temperature
T_BLK
-40
-
125
°C
Conditions
Electrical Specifications @ V_DD = 5V (unless otherwise specified):
Parameter
Symbol Min Typ Max Units
Conditions
Block Power Loss c
P_LOSS
-
9.4 11.7
W
V_IN=12V, V_OUT=1.3V
Turn On Delay d
Turn Off Delay d
t_d(on)
t_d(off)
-
63
-
I_OUT=40A, f_SW=1MHz
ns
-
26
-
L = 0.3µH
V_IN Quiescent Current
V_DD Quiescent Current
I_Q-VIN
-
-
1.0
mA ^{Enable = 0V, VIN=12V}
I_Q-VDD
-
10
-
µA ^{Enable = 0V, VDD=5V}
Under-Voltage Lockout
UVLO
Start Threshold
V_START
4.2
4.4
4.5
V
Hysteresis
V_Hvs-UVLO
-
150
-
mV
Enable
ENABLE
Input Voltage High
V_IH
2.1
-
-
V
Input Voltage Low
V_IL
-
-
0.8
Power Ready
PRDY
Logic Level High
Logic Level Low
V_OH
V_OL
4.5
4.6
-
-
0.1
0.2
V
V_DD=4.6V, I_Load=10mA
V_DD <UVLO Threshold, I_Load = 1mA
PWM Input
PWM
Logic Level High
V_OH
2.1
-
-
V
Logic Level Low
V_OL
-
-
0.8
 Measurement made using six 10uF (TDK C3225X5R1C106KT or equiv.) capacitors across the input (see
Fig. 8).
‚ Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
2
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