IP2003APBF Datasheet, PDF (1/10 Pages) International Rectifier – Synchronous Buck Multiphase Optimized LGA Power Block Intergrated Power Semiconductors,Drivers&Passives

PD-97051A
iP2003APbF
Synchronous Buck
Multiphase Optimized LGA Power Block
Features:
Integrated Power Semiconductors, Drivers & Passives
• Full function multiphase building block
• Output current 40A continuous with no derating up to
T_PCB = 100°C and T_CASE = 100°C
• Operating frequency up to 1.0 MHz
• Proprietary packaging enables ultra low Rth_{j-case top}
• Efficient dual sided cooling
• Small footprint low profile (9mm x11mm x 2.2mm) package
• Optimized for very low power losses
• LGA interface
• Ease of design
iP2003APbF Power Block
Description
The iP2003APbF is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 9mm x 11mm x 2.2mm
power block. The only additional components required for a complete multiphase converter are a PWM
controller, the output inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component integration
offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for
layout, heat transfer and component selection.
Pin # Pin Name
Pin Function
iP2003APbF Internal Block Diagram
1
V_DD Supply voltage for the internal circuitry.
When set to logic level high, internal circuitry
V_SWS1
V_SWS2
of the device is enabled. When set to logic
2
ENABLE level low, the PRDY pin is forced low, the
Control and Sychronous switches are turned
off, and the supply current reduces to 10µ A.
PRDY
V_IN
3
PW M TTL-level input signal to M OSFET drivers.
Power Ready - This pin indicates the status of
ENABLE
PWM
V_DD
MOSFET
Driver with
dead time
control
ENABLE or V_DD. This output will be driven
low when ENABLE is logic low or when V_DD
V_SW
4
PRDY is less than 4.4V (typ.). W hen ENABLE is
logic high and V_DD is greater than 4.4V (typ.),
this output is driven high. This output has a
10mA source and 1mA sink capability.
PGND
5, 7
6
PACKAGE
INTERFACE
PARTS
PARTS
PER
T&R
8
DESCRIPTION CONNECTION PER BAG
ORIENTATION
REEL
9
iP2003APbF
LGA
10
---
Fig 12
iP2003ATRPbF
LGA
---
1000
10
www.irf.com
8/16/06
PGND
V _SW
V _IN
V _SWS1
V _SWS2
Power Ground - connection to the ground of
bulk and filter capacitors.
Switching Node - connection to the output
inductor.
Input voltage pin. External bypass ceramic
capacitors must be added directly next to the
block.
Floating pin. For internal use. Externally, short
to V_SWS2 pin only_.
Floating pin. For internal use. Externally, short
to V_SWS1 pin only_.
1